1. Technical Field
The present invention relates to a semiconductor device and a method for manufacturing thereof, and more particularly relates to a multiple-layered semiconductor device composed of two or more stacked semiconductor packages, and a method for manufacturing thereof.
2. Related Art
Technologies for three-dimensionally stacking a plurality of semiconductor packages, each of which includes logic elements and memory circuit elements installed therein, attract attentions as semiconductor package technologies that can achieve higher integration levels and multiple-functioning capabilities of semiconductor devices. Semiconductor devices having such three-dimensional multiple-layered structure are generally referred to as package on package (PoP) or stack package.
Since the PoP structure provides a capability of selecting desired combinations of logic circuits and memory circuits in accordance with applications in the and also provides a capability of three-dimensionally stacks the selected elements, a reduction in effective dimensional area can be achieved. Thus, such structure is generally employed for smaller, thinner and multiple-functioning devices represented by portable telephones or the like.
An example of a cross-sectional structure according to a conventional PoP structure is shown in FIG. 10. A first semiconductor package 300 disposed as a lower layer includes a semiconductor device 312 flip-chip coupled onto a substrate 311 that includes coupling lands 314 in a circumference portion thereof, and a space between the substrate 311 and the semiconductor device 312 is filled with an underfill resin 313. Ball electrodes 317 serving as external coupling terminals are formed on the back surface of the substrate 311.
A second semiconductor package 400 disposed as an upper layer includes a semiconductor device 312 on another substrate 311 that is coupled thereto by wire bonding, and is encapsulated with a resin 315. The first semiconductor package 300 is joined to the second semiconductor package 400 via solder bumps 319 to configure the PoP structure.
Typical conventional technologies related to the present invention are included in, for example, Japanese Patent Laid-Open No. 2004-289,002, Japanese Patent Laid-Open No. 2002-252,326 and Japanese Patent Laid-Open No. 2004-172,157.
In addition, Japanese Patent Laid-Open No. H6-268,101 (1994) discloses a typical technology related to a pin grid array (PGA) package, in which the whole semiconductor package is encapsulated with a resin and a plurality of openings extending from the surface of the package to the internal lead frame surface are formed. Further configuration is also disclosed therein, which includes a stack of a plurality of packages formed through electro-conductive bumps provided in the openings.
Meanwhile, since these openings are provided for the purpose of providing a multiple-pin package that achieves an improved mass productivity and since such technology is related to the PGA package, the semiconductor device is installed on a tab, and is not provided on the thin substrate of the present invention.
In the above-described conventional technologies, the following problems are caused.
In order to achieve smaller and thinner devices that are required for the PoP structure, it is necessary to provide a thinner substrate and/or a thinner semiconductor device, which are component of the package.
However, the stiffness of the substrate depends upon the thickness of the substrate, and thus thinner substrate exhibits lower stiffness. Lower stiffness of the substrate possibly leads to a generation of a warpage. In addition to above, the substrate employed here includes an interconnect layer that connects coupling terminals on the front surface to coupling terminals on the back surface, and further includes an interposer.
A cross-sectional view for describing the problems in the conventional technology is shown in FIGS. 11A and 11B. FIG. 11A shows a first semiconductor package 300 and a second semiconductor package 400 in a condition before stacking and coupling. The first semiconductor package 300 provides a flip-chip coupling of a semiconductor device 312 onto a substrate 311 having coupling lands 314, and a gap between the substrate 311 and the semiconductor device 312 is filled with an underfill resin 313. The second semiconductor package 400 shown here as an example includes the semiconductor device 312 coupled by wire bonding.
In general, the whole semiconductor device 312 and a circumference thereof are encapsulated with a resin in processes for manufacturing the semiconductor device, for the purpose of providing a protection of the semiconductor device 312. The presence of such resin causes a shrinkage stress in a cure process after a supply of the resin, leading to a warpage in the substrate 311 of the first semiconductor package 300 as shown in FIG. 11A.
Thus, since a warpage is generated in the first semiconductor package 300, a defective situation such as a generation of coupling defectives 327 may be caused between the solder bumps 319 and the coupling land 314 of the first semiconductor package 300, when the first semiconductor package 300 is stacked to and coupled to the second semiconductor package 400 via electric conductors such as solder bumps 319 as shown in FIG. 11B, causing a problem of considerably deteriorating reliability for multiple-layered type semiconductor devices.